1. Field of the Invention
The present invention relates generally to processes and methods for fabricating electronic devices from semiconductor materials. More particularly, the present invention pertains to methods and apparatus offering improved process control for fabricating electronic devices having substrates of reduced thickness and enhanced quality.
2. State of the Art
The manufacture of semiconductor devices, commonly termed “dice” or “chips,” encompasses a plurality of major manufacturing stages, each of which typically comprises a number of elements. In general, chip manufacture may be generalized as comprising the stages of crystal growth, wafer preparation, wafer fabrication, wafer sort, and packaging. Wafer sort and packaging may be performed in a different order, or combined into a single manufacturing stage. Typically, a wafer of a semiconductor material such as silicon is cut from a large crystal and may have a nominal diameter of up to about 300 mm (12 inches). Although larger bulk semiconductor substrates may have been fabricated, the 300 mm wafer is the largest-size wafer currently being phased into commercial production runs by various semiconductor device manufacturers. As cut from a cylinder of semiconductor material transverse to the longitudinal axis thereof, a wafer typically has a thickness considerably greater than the usual end product of the semiconductor fabrication, i.e., singulated semiconductor dice. While a designated active surface of a wafer is repeatedly planarized following applications of various material layers during the fabrication of integrated circuitry thereon, the back side surface is generally left relatively rough, requiring a bulk material removal operation to remove extraneous material to thin the wafer and, optionally, a planarization step to reduce the roughness of the back side surface. For example, a wafer having an initial thickness prior to fabrication of integrated circuitry thereon of about 28 mils may be thinned to a final thickness of about 4 mils.
The fabrication stage of IC production is concentrated on the “active” surface of the wafer, which is relatively planar. Electrical components such as transistors, resistors, capacitors and the like; as well as interconnecting conductors, i.e., metallization; are formed on the active surface during the wafer fabrication stage. On the other hand, the role of the back side surface of the wafer, if any, is typically that of a mounting surface used to attach an individual semiconductor die to a carrier substrate of some sort. For example, the back side of a semiconductor die may be attached to a lead frame paddle, to an interposer, to a circuit board, to another die, or to some other substrate. In other instances, such as in the case of leads-over-chip packaging or in certain chip-scale packaging configurations, the back side of a semiconductor die may be encapsulated or merely coated. However, as package sizes have decreased, reduction in die (and thus wafer) thickness has been emphasized to reduce the thickness of the resulting packaged electronic device. Wafer thinning and planarization of the back side are required to reduce the wafer thickness to a desired dimension and provide a desired surface smoothness. The continual goal of producing integrated circuits of greater density (memory or logic components per unit volume) necessitates that semiconductor dice be of minimal thickness while retaining sufficient resistance to breakage, warping, electrical degradation and dislocation formation. It is anticipated that reducing wafer thickness to the range of 2 mils or less will become commercially feasible in the near future.
Current methods of removing material from a surface of a semiconductor substrate include wet etching using a liquid etchant, dry etching using a dry etchant, sputter-etching to physically remove material, mechanical abrasion or polishing by surface grinding using an abrasive grinding element in the form of a wheel or pad in combination with an abrasive slurry, chemical-mechanical planarization (CMP) by pad buffing in the presence of abrasive particles and an etchant and, of course, sequential combinations of the above individual techniques.
There are various methods of planarization. Planarization of a semiconductor substrate active surface to a smooth plane may be effected by forming a layer of material and removing same by one or more thinning processes. For example, continuous or discontinuous formation of a layer of silicon dioxide on a silicon surface and removal thereof may be repeated until a smooth, planar surface of silicon is produced. Planarization may also be achieved by tailoring one or more of the thinning methods to form a final, smooth, planar surface.
When conventional material removal techniques, such as those referenced above are applied to the thinning and planarization of a wafer back side, deficiencies are exhibited due to the initial roughness and nonplanarity of the back side surface produced when the wafer is severed from the cylinder of semiconductor material. Chemical thinning processes, e.g., wet etches and dry etches, remove substrate material at substantially the same rate in a direction normal to the surface, whether the surface portion in question is on a “peak” or in a “valley.” Thus, the finally thinned surface will have a generally similar topography but with reduced amplitude. In this application, “amplitude” is defined as the vertical distance between the point of greatest penetration from a mean surface level and the point of greatest elevation above the mean surface level.
In the case of a physical thinning process, e.g., abrasive grinding, it has been found that the lateral abrasive forces impinging upon the sides of “peaks” and “valleys” cause fracture and breakage below the valley levels. High-asperity-induced particles are produced, leading to further nonuniformities in removal rate. In addition, backgrinding wafers using conventional diamond grinding wheels may exacerbate the occurrence of flaws in the back side of a wafer.
It is desirable that the back side surface of the substrate be carefully thinned in a planar manner thereacross, particularly when nearing the end point of the thinning operation wherein a final substrate thickness is reached. However, localized stresses may cause wafer cracking, breakage, warpage and the like, particularly in the case of a very thin substrate. The thinning process is complicated by any warpage of the wafer occurring responsive to internal substrate stresses as the wafer is thinned. Such warpage may cause nonplanarity of the back side surface as thinning continues and is difficult to compensate for. As wafers are thinned to an ever-greater extent, the tendency to warp is exacerbated as stresses induced by fabrication of the integrated circuitry on the active surface of the wafer become more significant.
Various methods are known which are suitable for applying a layer of polymeric or other material to a substrate surface, such as a wafer active surface. A nonexhaustive list of such processes includes screen-coating, stencil-coating, spin-coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In the so-called Parylene™ process, a dimer molecule is heated to form a monomer vapor, which then deposits on a surface as a polymer at low (ambient) temperature.
The thinning and planarizing of the back side of a semiconductor wafer and the like by conventional techniques leaves much to be desired, in as much as such techniques fail to uniformly produce the desired planarity and smoothness. Improved methods for thinning and planarizing the back sides of semiconductor wafers and other substrates would be desirable from the standpoint of improved process control and quality enhancement in the final product.